LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY top_test IS END top_test; ARCHITECTURE behavior OF top_test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT top PORT( pb1 : IN std_logic; pb2 : IN std_logic; switch : IN std_logic_vector(3 downto 0); led : OUT std_logic_vector(4 downto 0); mode : OUT std_logic_vector(2 downto 0) ); END COMPONENT; --Inputs signal pb1 : std_logic := '0'; signal pb2 : std_logic := '0'; signal switch : std_logic_vector(3 downto 0) := (others => '0'); --Outputs signal led : std_logic_vector(4 downto 0); signal mode : std_logic_vector(2 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: top PORT MAP ( pb1 => pb1, pb2 => pb2, switch => switch, led => led, mode => mode ); -- Stimulus process stim_proc: process begin -- hold reset state for 50 ns. wait for 50 ns; -- insert stimulus here -- F switch <= "0100"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; switch <= "0110"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 15ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; -- P switch <= "0101"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; switch <= "0000"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 15ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; -- G switch <= "0100"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; switch <= "0111"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 15ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; -- A switch <= "0100"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; switch <= "0001"; wait for 10ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 15ns; pb1 <= '1'; wait for 5ns; pb1 <= '0'; wait for 5ns; end process; END;
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