library ieee; use ieee.std_logic_1164.all; entity SHIFT_BARREL is port( DATA_in: in std_logic_vector(7 downto 0); -- insert DATA to register SEL: in std_logic; -- stanga sau dreapta SHIFT_NR: in std_logic_vector(1 downto 0); DATA_out: out std_logic_vector(7 downto 0)); end SHIFT_BARREL; architecture SHIFT_arch of SHIFT_BARREL is signal DATA_1: std_logic_vector(7 downto 0); signal DATA_2: std_logic_vector(7 downto 0); begin SHIFT_LEFT: process(DATA_in, SHIFT_NR) variable temp_1: std_logic_vector(7 downto 0); variable temp_2: std_logic_vector(7 downto 0); begin case SHIFT_NR(0) is when '1' => temp_1 := DATA_in(6 downto 0) & '0'; when '0' => temp_1 := DATA_in; when others => null; end case; case SHIFT_NR(1) is when '1' => temp_2 := temp_1(5 downto 0) & "00"; when '0' => temp_2 := temp_1; when others => null; end case; DATA_1 <= temp_2; end process SHIFT_LEFT; SHIFT_RIGHT: process(DATA_in, SHIFT_NR) variable temp_1: std_logic_vector(7 downto 0); variable temp_2: std_logic_vector(7 downto 0); begin case SHIFT_NR(0) is when '1' => temp_1 := '0' & DATA_in(7 downto 1); when '0' => temp_1 := DATA_in; when others => null; end case; case SHIFT_NR(1) is when '1' => temp_2 := "00" & temp_1(7 downto 2); when '0' => temp_2 := temp_1; when others => null; end case; DATA_2 <= temp_2; end process SHIFT_RIGHT; WITH SEL SELECT DATA_out <= DATA_1 when '0', DATA_2 when others; end SHIFT_arch;
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