Pasted

NOTE: mixing pins from different iosets of the same spi peripheral is not forbidden but may
result in sub-optimal timing, i.e. it may reduce the maximum bus speed that works reliably.
ioset probably doesn't matter for chip select pins.
                       sclk      d0/miso   d1/mosi   cs0       cs1       cs2       cs3         
 mcspi 2               P9.22b    P9.18a    P9.21b    P9.17a    P9.23     -         -           
 mcspi 3 ioset 1       P8.35b    -         P8.33b    P9.21a    P8.06     -         -           
mcspi 3 ioset 2       P8.27a    P8.29a    P8.30a    P8.28a    -         P8.45a    P8.46b      
mcspi 3 ioset 3       P9.31a    P9.30     P9.29a    P9.28     P9.42a    P8.45a    P8.46b      
mcspi 3 ioset 4       P8.38b    P8.31b    P8.37b    P8.32b    -         P8.45a    P8.46b      
mcspi 3 ioset 5       P8.20     P8.24     P8.25     P8.05     P8.06     -         -           
 mcspi 4 ioset 2       -         P8.36b    P8.34b    -         -         -         -           
mcspi 4 ioset 5       P8.23     P8.03     P8.22     P8.04     -         -         -