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MIPS MEMWB Buffer

Perrine | PRO | 11/26/12 08:29:17 PM UTC | 0 ⭐ | 5378 👁️ | Never ⏰ | []
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module MEMWB(mem_control, mem_data, mem_address, mem_ALU,
                wb_control, wb_data, wb_address, wb_ALU);
    
    input mem_control, mem_data, mem_address, mem_ALU;
    output wb_control, wb_data, wb_address, wb_ALU;
    
    wire[1:0] mem_control;
    wire[4:0] mem_address;
    wire[31:0] mem_ALU, mem_data;
    
    reg[1:0] int_control;
    reg[4:0] int_address;
    reg[31:0] int_ALU, int_data;
    
    reg[1:0] wb_control;
    reg[4:0] wb_address;
    reg[31:0] wb_ALU, wb_data;
    
    always@(posedge clk) begin
        int_control = mem_control;
        int_address = mem_address;
        int_ALU = mem_ALU;
        int_data = mem_data;
    end
    
    always@(negedge clk) begin
        wb_control = int_control;
        wb_address = int_address;
        wb_ALU = int_ALU;
        wb_data = int_data;
    end
endmodule

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