library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity NUMARATOR is port( CE: in std_logic; CLK: in std_logic; DATA_in: in std_logic_vector(3 downto 0); PL: in std_logic; RESET: in std_logic; TC: out std_logic; DATA_out: out std_logic_vector(3 downto 0)); end NUMARATOR; architecture NUMARATOR_arch of NUMARATOR is begin NUMARATOR_10: process(CLK, RESET, PL) variable count: std_logic_vector(3 downto 0) := (others => '0'); begin TC <= '0'; if(RESET = '0') THEN count := (others => '0'); ELSIF (PL = '0') THEN count := DATA_in; ELSIF (rising_edge(CLK)) THEN IF(CE = '1') THEN IF(count = "1001") THEN count := (others => '0'); ELSE count := count+1; END IF; END IF; END IF; IF(count = "1001") THEN TC <= '1'; END IF; DATA_out <= count; end process NUMARATOR_10; end NUMARATOR_arch;
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