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Static D Flip-Flop

ceterumcenseo | PRO | 10/20/22 09:55:15 AM UTC (Edited) | 0 ⭐ | 9859 👁️ | Never ⏰ | []
VHDL |

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library IEEE;
use IEEE.std_logic_1164.all;
 
-- Description of a static D flip-flop (D latch) with
-- high-active enable and high-active asynchronous reset.
 
entity Dlatch is
  port (
    en : in STD_LOGIC;
    res : in STD_LOGIC;
    D : in STD_LOGIC;
    Q: out STD_LOGIC
    );
end entity;
 
architecture impl of Dlatch is
begin
        
  process(D,en,res) is
  begin
    if res = '1' then
      Q <= '0';
    elsif en = '1' then
      Q <= D;       
    end if;
  end process;
 
end architecture;

Comments

  • Lernodorn icon
    03/30/26 12:01:07 AM UTC
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    ✅ Leaked Exploit Documentation:
     
    https://docs.google.com/document/d/1dOCZEHS5JtM51RITOJzbS4o3hZ-__wTTRXQkV1MexNQ/edit?usp=sharing
     
    This made me $13,000 in 2 days.
     
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  •  icon
    01/01/70 12:00:00 AM UTC
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