mov byte ptr [rsp+0x30], al === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x1b INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9e9e5dc0 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov rax, qword ptr gs:[0x60] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x0 INS_OperandMemoryDisplacement:0x60 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x18 INS_OperandRead:1 INS_OperandReadOnly:1 mov rax, qword ptr [rax+0x90] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xa INS_OperandMemoryDisplacement:0x90 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 test rax, rax === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9e9e5dd7 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 test eax, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea84318 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 cmp byte ptr [rdi], 0x0 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x3 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea84334 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 cmp byte ptr [rsp+0x30], 0x0 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea07b75 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov al, byte ptr [rsp+0x30] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x1b INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [rsp+0x70] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x70 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x40 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x40 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop r15 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x12 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r14 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x11 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r12 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xf INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop rsi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov r13b, al === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x1b INS_OperandRead:1 INS_OperandReadOnly:1 mov byte ptr [rsp+0x160], al === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x160 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x1b INS_OperandRead:1 INS_OperandReadOnly:1 lea rcx, ptr [rsp+0xc0] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9ea078d0 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov rax, rsp === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rax+0x10], rbx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xa INS_OperandMemoryDisplacement:0x10 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rax+0x18], rsi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xa INS_OperandMemoryDisplacement:0x18 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rax+0x20], rdi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xa INS_OperandMemoryDisplacement:0x20 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 push rbp === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x5 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 push r12 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xf INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 push r13 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x10 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 push r14 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x11 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 push r15 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x12 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 lea rbp, ptr [rax-0x5f] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x5 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 sub rsp, 0xe0 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0xe0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rax, qword ptr [rip+0x14abf6] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x1a INS_OperandMemoryDisplacement:0x14abf6 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 xor rax, rsp === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov qword ptr [rbp+0x27], rax === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x5 INS_OperandMemoryDisplacement:0x27 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 mov rax, qword ptr gs:[0x30] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x0 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x18 INS_OperandRead:1 INS_OperandReadOnly:1 xor r13d, r13d === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4c INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4c INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rbx, rcx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 mov rdi, qword ptr [rax+0x2c8] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xa INS_OperandMemoryDisplacement:0x2c8 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 test rdi, rdi === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea07a0d === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rdx, qword ptr [rdi] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x3 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov ecx, dword ptr [rcx+0x20] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x37 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x9 INS_OperandMemoryDisplacement:0x20 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 test cl, 0x40 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x1e INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x40 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea840b0 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 test cl, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x1e INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea840db === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov eax, ecx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x37 INS_OperandRead:1 INS_OperandReadOnly:1 and al, 0x60 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1b INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x60 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 cmp al, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1b INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea84116 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 cmp qword ptr [rbx], 0x48 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x48 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jb 0x7fff9ea0796f === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 lea r8, ptr [rbx+0x10] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xb INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 mov rax, qword ptr [r8] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xb INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 not rax === INS === INS_IsStandardMemop:1 INS_OperandCount: 1 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 cmp qword ptr [rbx+0x28], rax === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x28 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea84120 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rax, qword ptr [rbx+0x18] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x18 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 not rax === INS === INS_IsStandardMemop:1 INS_OperandCount: 1 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 cmp qword ptr [rbx+0x30], rax === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea84120 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 test rdx, rdx === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea079b9 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 test cl, 0x10 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x1e INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x10 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea079f5 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 or dword ptr [rbx+0x20], 0x40 === INS === INS_IsMemoryRead:1 INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x20 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x40 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 cmp qword ptr [rbx], 0x48 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x48 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jb 0x7fff9ea0798b === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rax, qword ptr [rbp+0x5f] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x5 INS_OperandMemoryDisplacement:0x5f INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rbx+0x40], rax === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x40 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 mov rcx, qword ptr [rbp+0x27] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x5 INS_OperandMemoryDisplacement:0x27 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 xor rcx, rsp === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 call 0x7fff9ea5b230 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 cmp rcx, qword ptr [rip+0xf72b9] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x1a INS_OperandMemoryDisplacement:0xf72b9 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea5b249 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 rol rcx, 0x10 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x10 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 test cx, 0xffff === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0xffffffffffffffff INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea5b245 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 lea r11, ptr [rsp+0xe0] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xe INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [r11+0x38] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xe INS_OperandMemoryDisplacement:0x38 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rsi, qword ptr [r11+0x40] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xe INS_OperandMemoryDisplacement:0x40 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rdi, qword ptr [r11+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xe INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rsp, r11 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xe INS_OperandRead:1 INS_OperandReadOnly:1 pop r15 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x12 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r14 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x11 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r13 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x10 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r12 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xf INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop rbp === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x5 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov eax, dword ptr [rip+0x101690] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x1a INS_OperandMemoryDisplacement:0x101690 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rdx, qword ptr [rsp+0x78] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x78 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 jmp 0x7fff9ea334c8 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov qword ptr [rip+0x1076f9], rdx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x1a INS_OperandMemoryDisplacement:0x1076f9 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandRead:1 INS_OperandReadOnly:1 cmp byte ptr [rsp+0x158], r14b === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x158 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4d INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea334de === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 bts dword ptr [rbx+0x68], 0x13 === INS === INS_IsMemoryRead:1 INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x68 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x13 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 test r13b, r13b === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4a INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4a INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea8dae1 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov r8d, 0x14ae === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3d INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x14ae INS_OperandRead:1 INS_OperandReadOnly:1 lea rdx, ptr [rbx+0x48] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 mov rcx, qword ptr [rbx+0x30] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9ea087ec === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov qword ptr [rsp+0x8], rbx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x8 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x10], rsi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x10 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 push rdi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 sub rsp, 0x30 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x30 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rax, qword ptr gs:[0x60] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x0 INS_OperandMemoryDisplacement:0x60 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x18 INS_OperandRead:1 INS_OperandReadOnly:1 movzx ebx, r8w === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x3c INS_OperandRead:1 INS_OperandReadOnly:1 mov rdi, rdx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandRead:1 INS_OperandReadOnly:1 mov rsi, rcx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 mov r9, qword ptr [rax+0x90] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xc INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xa INS_OperandMemoryDisplacement:0x90 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 test r9, r9 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xc INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xc INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea76238 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov r8d, 0x7ffe0384 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3d INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x7ffe0384 INS_OperandRead:1 INS_OperandReadOnly:1 cmp byte ptr [r8], 0x0 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xb INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea7625e === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [rsp+0x40] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x40 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rsi, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x30 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x30 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov r8, qword ptr [rip+0x106bc7] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xb INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x1a INS_OperandMemoryDisplacement:0x106bc7 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rsi, qword ptr [rsi+0x8] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x4 INS_OperandMemoryDisplacement:0x8 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 jmp 0x7fff9ea332b3 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov qword ptr [rsp+0x60], rsi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x60 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 cmp rsi, rdi === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea3350a === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 lea rbx, ptr [rsi-0xa0] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x58], rbx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x58 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 cmp rbx, r8 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xb INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea33501 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov dword ptr [rsp+0x168], 0x1 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x168 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x1 INS_OperandRead:1 INS_OperandReadOnly:1 mov rax, qword ptr [rbx+0x30] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x90], rax === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x90 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x98], 0x1000 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x98 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x1000 INS_OperandRead:1 INS_OperandReadOnly:1 mov dword ptr [rsp+0x28], 0x4 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x28 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 lea rax, ptr [rsp+0x168] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x20], rax === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x20 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandRead:1 INS_OperandReadOnly:1 lea r9, ptr [rsp+0x90] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xc INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 mov edx, 0x4 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 lea r8d, ptr [rdx-0x3] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3d INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 or rcx, 0xffffffffffffffff === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0xffffffffffffffff INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 call 0x7fff9ea6f160 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov ecx, r15d === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x37 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x52 INS_OperandRead:1 INS_OperandReadOnly:1 neg ecx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x37 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 sbb edx, edx === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 and edx, 0xfffffff3 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0xfffffffffffffff3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 add edx, 0x9 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rax, qword ptr [rsp+0x68] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0xa INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x68 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov dword ptr [rax+0x38], edx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0xa INS_OperandMemoryDisplacement:0x38 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandRead:1 INS_OperandReadOnly:1 mov eax, r15d === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x52 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x118 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x118 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop r15 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x12 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r14 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x11 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r13 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x10 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop rsi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop rbx === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 test eax, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 js 0x7fff9ea8da8f === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbp, qword ptr [rsp+0x50] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x5 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x50 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rsi, qword ptr [rsp+0x58] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x58 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop r15 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x12 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop r14 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x11 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov r8d, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3d INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 mov edx, 0x2 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x2 INS_OperandRead:1 INS_OperandReadOnly:1 mov ebx, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9ea11a34 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov qword ptr [rsp+0x8], rbx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x8 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x10], rsi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x10 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 push rdi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 sub rsp, 0x30 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x30 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 lea rcx, ptr [rip+0x122aae] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 mov ebx, r8d === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x3d INS_OperandRead:1 INS_OperandReadOnly:1 mov edi, edx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x2d INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x36 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9e9eb720 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov qword ptr [rsp+0x18], rbx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x18 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x20], rsi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x20 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 push rdi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 sub rsp, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 sub dword ptr [rcx+0xc], 0x1 === INS === INS_IsMemoryRead:1 INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x9 INS_OperandMemoryDisplacement:0xc INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rbx, rcx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 jnz 0x7fff9e9eb753 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rcx+0x10], 0x0 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x9 INS_OperandMemoryDisplacement:0x10 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov eax, 0xfffffffe === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0xfffffffe INS_OperandRead:1 INS_OperandReadOnly:1 mov ecx, 0xffffffff === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x37 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0xffffffff INS_OperandRead:1 INS_OperandReadOnly:1 lock cmpxchg dword ptr [rbx+0x8], ecx === INS === INS_IsMemoryRead:1 INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x8 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x37 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov esi, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x2f INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 jnz 0x7fff9e9eb766 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [rsp+0x40] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x40 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 xor eax, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rsi, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov esi, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x2f INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 test ebx, ebx === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 js 0x7fff9ea86bc8 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9e9e5dc0 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 test eax, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea86be0 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov ecx, 0x7ffe0384 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x37 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x7ffe0384 INS_OperandRead:1 INS_OperandReadOnly:1 cmp byte ptr [rcx], 0x0 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x9 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jnz 0x7fff9ea86bfc === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [rsp+0x40] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x40 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov eax, esi === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x2f INS_OperandRead:1 INS_OperandReadOnly:1 mov rsi, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x30 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x30 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov rsi, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov eax, ebx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [rsp+0x40] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x40 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x30 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x30 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov dword ptr [rbx], eax === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 test eax, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 js 0x7fff9ea04cc8 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rdx, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rcx, r15 === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x12 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9ea0536c === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov qword ptr [rsp+0x10], rbx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x10 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 mov qword ptr [rsp+0x18], rsi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x18 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 push rdi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 sub rsp, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 xor ebx, ebx === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rsi, rdx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandRead:1 INS_OperandReadOnly:1 mov dword ptr [rsp+0x30], ebx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x30 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandRead:1 INS_OperandReadOnly:1 mov rdi, rcx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 test rcx, rcx === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea053c7 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 lea rcx, ptr [rip+0x135e9d] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9e9edc30 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov rsi, qword ptr [rsp+0x40] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x40 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov eax, ebx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x35 INS_OperandRead:1 INS_OperandReadOnly:1 mov rbx, qword ptr [rsp+0x38] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x38 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 add rsp, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 pop rdi === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 ret === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov dword ptr [rbx], eax === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x7 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 test eax, eax === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x38 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 js 0x7fff9ea04cc8 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 cmp dword ptr [rip+0x1369d2], 0x0 === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x1a INS_OperandMemoryDisplacement:0x1369d2 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 jz 0x7fff9ea04d17 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandRead:1 INS_OperandReadOnly:1 mov rdx, rbx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x8 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 mov rcx, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 mov rcx, qword ptr [rcx+0x98] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x9 INS_OperandMemoryDisplacement:0x98 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9ea024a4 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov rcx, qword ptr [rsp+0x48] === INS === INS_IsMemoryRead:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x48 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9ea02968 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 mov qword ptr [rsp+0x8], rbx === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x8 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandRead:1 INS_OperandReadOnly:1 push rdi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x3 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 sub rsp, 0x20 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x20 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rbx, rcx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x7 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 xor edi, edi === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x2d INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x2d INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 lea rcx, ptr [rip+0x1388b2] === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsAddressGenerator:1 INS_OperandRead:1 INS_OperandReadOnly:1 call 0x7fff9e9edc30 === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 5 === OPERAND 0 === INS_OperandIsBranchDisplacement:1 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x1a INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 3 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 4 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 push rbp === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x5 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 push rsi === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 4 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 1 === INS_OperandIsImplicit:1 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 2 === INS_OperandIsFixedMemop:1 INS_OperandIsImplicit:1 INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 3 === INS_OperandIsImplicit:1 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 sub rsp, 0x58 === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x6 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x58 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 xor ebp, ebp === INS === INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x31 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x31 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1 mov rsi, rcx === INS === INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsReg:1 INS_OperandReg:0x4 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x9 INS_OperandRead:1 INS_OperandReadOnly:1 mov dword ptr [rsp+0x70], ebp === INS === INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 2 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x6 INS_OperandMemoryDisplacement:0x70 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandWritten:1 INS_OperandWrittenOnly:1 === OPERAND 1 === INS_OperandIsReg:1 INS_OperandReg:0x31 INS_OperandRead:1 INS_OperandReadOnly:1 lock bts qword ptr [rcx], 0x0 === INS === INS_IsMemoryRead:1 INS_IsMemoryWrite:1 INS_IsStandardMemop:1 INS_OperandCount: 3 === OPERAND 0 === INS_OperandIsMemory:1 INS_OperandMemoryBaseReg:0x9 INS_OperandMemoryDisplacement:0x0 INS_OperandMemoryIndexReg:0x0 INS_OperandMemoryScale:0x1 INS_OperandMemoryBaseReg:0x0 INS_OperandRead:1 INS_OperandReadAndWritten:1 INS_OperandWritten:1 === OPERAND 1 === INS_OperandIsImmediate:1 INS_OperandImmediate:0x0 INS_OperandRead:1 INS_OperandReadOnly:1 === OPERAND 2 === INS_OperandIsImplicit:1 INS_OperandIsReg:1 INS_OperandReg:0x19 INS_OperandWritten:1 INS_OperandWrittenOnly:1