#include "am57xx-beagle-x15-revc.dts"
#include "bbx15-pins.h"  // https://pastebin.com/raw/tGcpaiyg
#include "bbx15-gpios.h"  // https://pastebin.com/raw/rELLdW1k

&{/chosen} {
	base_dtb = "am57xx-beagle-x15-custom.dts";  // <-- fill in name of this file
	base_dtb_timestamp = __TIMESTAMP__;
};


// uncomment this line if you want the two ethernet ports to be connected via
// internal switch instead of being two independent ports:
&mac {  /delete-property/ dual_emac;  };


//====== EXAMPLE: gpios ======================================
//
// For more documentation about gpio-of-helper see:
//   https://github.com/mvduin/overlay-utils/blob/master/gpio-demo.dtsi
// (but note that this is for the BBB and uses different pinmux syntax)

/ {
	// Any name is fine as long as it doesn't conflict with existing nodes
	gpio-demo {
		compatible = "gpio-of-helper";

		pinctrl-names = "default";
		pinctrl-0 = <&gpio_demo_pins>;

		P16.36 {
			gpio = <P16_36_GPIO GPIO_ACTIVE_HIGH>;
			input;
			dir-changeable;
		};

		P16.43 {
			gpio = <P16_43_GPIO GPIO_ACTIVE_HIGH>;
			input;
			dir-changeable;
		};
	};
};

&dra7_pmx_core {
	gpio_demo_pins: gpio-demo {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD( P16_36, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P16.36 / gpio 6.03
			DRA7XX_CORE_IOPAD( P16_43, PIN_INPUT_PULLDOWN | MUX_MODE14 )  // P16.43 / gpio 6.04
		>;
	};
};


//====== EXAMPLE: eCAP pwm output ======================================

// enable subsystem containing ecap0
&epwmss0 {
	status = "okay";
};

// enable ecap0 and configure its pin
&ecap0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ecap0_pins>;
};

&dra7_pmx_core {
	// pin config block for ecap0
	ecap0_pins: ecap0 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD( P18_12,  PIN_OUTPUT_PULLDOWN | MUX_MODE10 )  // P18.12 ecap0
		>;
	};
};


//====== EXAMPLE: spi ==================================================

&mcspi3 {
	// enable spi controller and mux pins:
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi3_pins>;

	// create spi slave device for chip select 0:
	spidev@0 {
		reg = <0>;
		compatible = "spidev";
		spi-max-frequency = <24000000>;
		spi-cpol; spi-cpha;  // configure spi mode 3 by default

		symlink = "spi/2.0";  // create symlink at /dev/spi/2.0
	};

	// create spi slave device for chip select 1:
	spidev@1 {
		reg = <1>;
		compatible = "spidev";
		spi-max-frequency = <24000000>;
		spi-cpol; spi-cpha;  // configure spi mode 3 by default

		symlink = "spi/2.1";  // create symlink at /dev/spi/2.1
	};
};

&dra7_pmx_core {
	mcspi3_pins: mcspi3 {
		// choose an option:
#if 1
		// spi 2 ioset 4
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD( P16_34, PIN_INPUT_PULLUP  | MUX_MODE3 )  // P16.34  spi 2 clk
			DRA7XX_CORE_IOPAD( P16_04, PIN_OUTPUT_PULLUP | MUX_MODE3 )  // P16.04  spi 2 d1 (mosi)
			DRA7XX_CORE_IOPAD( P16_33, PIN_INPUT_PULLUP  | MUX_MODE3 )  // P16.33  spi 2 d0 (miso)
			DRA7XX_CORE_IOPAD( P16_03, PIN_OUTPUT_PULLUP | MUX_MODE3 )  // P16.03  spi 2 cs0
			DRA7XX_CORE_IOPAD( P16_05, PIN_OUTPUT_PULLUP | MUX_MODE3 )  // P16.05  spi 2 cs1
		>;
#else
		// spi 2 ioset 6
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD( P17_04, PIN_INPUT_PULLUP  | MUX_MODE1 )  // P17.04  spi 2 clk
			DRA7XX_CORE_IOPAD( P17_07, PIN_OUTPUT_PULLUP | MUX_MODE1 )  // P17.07  spi 2 d1 (mosi)
			DRA7XX_CORE_IOPAD( P17_36, PIN_INPUT_PULLUP  | MUX_MODE1 )  // P17.36  spi 2 d0 (miso)
			DRA7XX_CORE_IOPAD( P17_08, PIN_OUTPUT_PULLUP | MUX_MODE1 )  // P17.08  spi 2 cs0
			DRA7XX_CORE_IOPAD( P17_33, PIN_OUTPUT_PULLUP | MUX_MODE1 )  // P17.33  spi 2 cs1
		>;
#endif
	};
};