1 Questions



1.1


process(clk_en,di,dsi,rstn)
begin
    if rstn='0' then
        do<=(others=>'0');
    elsif clk_en= '1'then
        if dsi='1'then
            do<=di;
        end if;
    end if;
end process;

- This process is a syncroeous process because the output does not only depent on the input, but also of the past values of inputs.
- Although the process does not contain any syntactical errors, the functionality is not useful. I think the process tries to implement a
  DFF with asyncroneus reset. Non-syntactical errors: clk signal not in sensitivity list and the DFF does not operate on rising edge of the clock.


Improved version:


process(clk ,clk_en,di,dsi,rstn)
begin
    if rising_edge(clk) then
        if rstn='0' then
            do<=(others=>'0');
        elsif clk_en= '1'then
            if dsi='1'then
                do<=di;
            end if;
        end if;
    end if;
end process;