- BLOCK_NAME: 'SMUIO' - DESCRIPTION: 'SMUIO Block SMUSVI registers' Registers: PWR_OVERRIDE (smn_addr_map:0x5a30c,iod_smn_addr_map:0x5a30c) 32bit: 0 VDDCR_VDD_OVERRIDE SMUIO_FORCE_SELFREFRESH (smn_addr_map:0x5a314,iod_smn_addr_map:0x5a314) 32bit: 0 PU 1 PD 2 OE 3 TXIMPSEL 4 RXSEL1 5 RXSEL0 6 RXEN 7 A 8 Y(R) SMUIO_MCM_CONFIG (smn_addr_map:0x5a08c,iod_smn_addr_map:0x5a08c) 32bit: 1:0 DIE_ID(R) 4:2 PKG_TYPE 5 SOCKET_ID(R) 7:6 PKG_SUBTYPE SMUIO_MP_RESET_INTR (smn_addr_map:0x5a304,iod_smn_addr_map:0x5a304) 32bit: 0 SMUIO_MP_RESET_INTR(R) SMUIO_NV_SAVE_N (smn_addr_map:0x5a310,iod_smn_addr_map:0x5a310) 32bit: 0 PU 1 PD 2 S0 3 S1 4 OE_OVERRIDE 5 OE 6 A_OVERRIDE 7 A 8 SCHMEN 9 Y(R) SMUIO_PWRMGT (smn_addr_map:0x5a31c,iod_smn_addr_map:0x5a31c) 32bit: 0 i2c_clk_gate_en 4 i2c1_clk_gate_en SMUIO_RESET_DELAY (smn_addr_map:0x5a318,iod_smn_addr_map:0x5a318) 32bit: 15:0 SMUIO_RESET_DELAY SMUIO_RESET_SEL (smn_addr_map:0x5a300,iod_smn_addr_map:0x5a300) 32bit: 0 SMUIO_RESET_SEL SMUIO_SOC_HALT (smn_addr_map:0x5a308,iod_smn_addr_map:0x5a308) 32bit: 2 WDT_FORCE_PWROK_EN 3 WDT_FORCE_RESETn_EN SMUSVI0_MISC_VID_STATUS (smn_addr_map:0x5a028,iod_smn_addr_map:0x5a028) 32bit: 7:0 MAX_VID(R) 17:10 MIN_VID(R) 30:23 SVI0_PLANE0_PSI_VID 31 SVI0_PLANE0_PSI_VID_EN SMUSVI0_PLANE0_CURRENTVID (smn_addr_map:0x5a050,iod_smn_addr_map:0x5a050) 32bit (R): 31:24 CURRENT_SVI0_PLANE0_VID SMUSVI0_PLANE0_LOAD (smn_addr_map:0x5a004,iod_smn_addr_map:0x5a004) 32bit: 4:0 SVI0_LOADLINE_PLANE0 5 SVI0_PSI1_PLANE0 SMUSVI0_PLANE0_TEL_IDD_SUM (smn_addr_map:0x5a0a4,iod_smn_addr_map:0x5a0a4) 32bit (R): 17:0 SVI0_PLANE0_TEL_IDD_SUM SMUSVI0_PLANE0_TEL_MAX (smn_addr_map:0x5a0b0,iod_smn_addr_map:0x5a0b0) 32bit (R): 7:0 SVI0_PLANE0_TEL_IDD_MAX 24:16 SVI0_PLANE0_TEL_VDD_MAX SMUSVI0_PLANE0_TEL_MIN (smn_addr_map:0x5a0ac,iod_smn_addr_map:0x5a0ac) 32bit (R): 7:0 SVI0_PLANE0_TEL_IDD_MIN 24:16 SVI0_PLANE0_TEL_VDD_MIN SMUSVI0_PLANE0_TEL_SAMPLE_CNT (smn_addr_map:0x5a0a0,iod_smn_addr_map:0x5a0a0) 32bit (R): 9:0 SVI0_PLANE0_TEL_SAMPLE_CNT SMUSVI0_PLANE0_TEL_VDD_SUM (smn_addr_map:0x5a0a8,iod_smn_addr_map:0x5a0a8) 32bit (R): 18:0 SVI0_PLANE0_TEL_VDD_SUM SMUSVI0_PLANE0_VIDCHGBUSY (smn_addr_map:0x5a040,iod_smn_addr_map:0x5a040) 32bit (R): 0 SVI0_PLANE0_VID_CHGBUSY SMUSVI0_PLANE1_CURRENTVID (smn_addr_map:0x5a058,iod_smn_addr_map:0x5a058) 32bit (R): 31:24 CURRENT_SVI0_PLANE1_VID SMUSVI0_PLANE1_LOAD (smn_addr_map:0x5a000,iod_smn_addr_map:0x5a000) 32bit: 4:0 SVI0_LOADLINE_PLANE1 5 SVI0_PSI1_PLANE1 8 SIDEBAND_PLANE0_CHGVID_EN 12 SIDEBAND_PLANE1_CHGVID_EN 16 SVI0_PLANE0_SIDEBAND_VID_CHGBUSY(R) 20 SVI0_PLANE1_SIDEBAND_VID_CHGBUSY(R) 24 SVI1_PLANE0_SIDEBAND_VID_CHGBUSY(R) 25 SVI1_PLANE1_SIDEBAND_VID_CHGBUSY(R) 26 SIDEBAND_OUTSTD_EN 29 WAITVIDCOMPDIS_SVI0 30 WAITVIDCOMPDIS_SVI1 31 SVIBUSY(R) SMUSVI0_PLANE1_TEL_IDD_SUM (smn_addr_map:0x5a0b8,iod_smn_addr_map:0x5a0b8) 32bit (R): 17:0 SVI0_PLANE1_TEL_IDD_SUM SMUSVI0_PLANE1_TEL_MAX (smn_addr_map:0x5a0c4,iod_smn_addr_map:0x5a0c4) 32bit (R): 7:0 SVI0_PLANE1_TEL_IDD_MAX 24:16 SVI0_PLANE1_TEL_VDD_MAX SMUSVI0_PLANE1_TEL_MIN (smn_addr_map:0x5a0c0,iod_smn_addr_map:0x5a0c0) 32bit (R): 7:0 SVI0_PLANE1_TEL_IDD_MIN 24:16 SVI0_PLANE1_TEL_VDD_MIN SMUSVI0_PLANE1_TEL_SAMPLE_CNT (smn_addr_map:0x5a0b4,iod_smn_addr_map:0x5a0b4) 32bit (R): 9:0 SVI0_PLANE1_TEL_SAMPLE_CNT SMUSVI0_PLANE1_TEL_VDD_SUM (smn_addr_map:0x5a0bc,iod_smn_addr_map:0x5a0bc) 32bit (R): 18:0 SVI0_PLANE1_TEL_VDD_SUM SMUSVI0_PLANE1_VIDCHGBUSY (smn_addr_map:0x5a044,iod_smn_addr_map:0x5a044) 32bit (R): 0 SVI0_PLANE1_VID_CHGBUSY SMUSVI0_PLANE_VIDCHG (smn_addr_map:0x5a030,iod_smn_addr_map:0x5a030) 32bit: 1:0 SVI0_VIDPLANE 5 SVI0_VIDCHGZEROVID 6 SVI0_VIDCHGRAMP 9:7 SVI0_VSTIME 23:16 SVI0_VID SMUSVI0_PWR_CTL_MISC (smn_addr_map:0x5a02c,iod_smn_addr_map:0x5a02c) 32bit: 6:0 SVI0_PLANE1_PSIVID 7 SVI0_PLANE1_PSIVIDEN 8 SVI0_PLANE1_PSIVID_HI 14 HIGHFREQSEL_SVI0 15 HIGHFREQSEL_SVI1 16 SVI0_SAMPLE_SVT_DLY_SEL 20 SVI1_SAMPLE_SVT_DLY_SEL SMUSVI0_TEL_PLANE0 (smn_addr_map:0x5a010,iod_smn_addr_map:0x5a010) 32bit (R): 7:0 SVI0_PLANE0_IDDCOR 24:16 SVI0_PLANE0_VDDCOR SMUSVI0_TEL_PLANE1 (smn_addr_map:0x5a00c,iod_smn_addr_map:0x5a00c) 32bit (R): 7:0 SVI0_PLANE1_IDDCOR 24:16 SVI0_PLANE1_VDDCOR SMUSVI0_TFN (smn_addr_map:0x5a008,iod_smn_addr_map:0x5a008) 32bit: 0 SVI0_TFN_PLANE0 1 SVI0_TFN_PLANE1 SMUSVI1_LOAD (smn_addr_map:0x5a01c,iod_smn_addr_map:0x5a01c) 32bit: 4:0 SVI1_LOADLINE_PLANE0 8 SVI1_PSI1_PLANE0 16:12 SVI1_LOADLINE_PLANE1 20 SVI1_PSI1_PLANE1 31 SVIBUSY1(R) SMUSVI1_PLANE0_CURRENTVID (smn_addr_map:0x5a054,iod_smn_addr_map:0x5a054) 32bit (R): 31:24 CURRENT_SVI1_PLANE0_VID SMUSVI1_PLANE0_TEL_IDD_SUM (smn_addr_map:0x5a0cc,iod_smn_addr_map:0x5a0cc) 32bit (R): 17:0 SVI1_PLANE0_TEL_IDD_SUM SMUSVI1_PLANE0_TEL_MAX (smn_addr_map:0x5a0d8,iod_smn_addr_map:0x5a0d8) 32bit (R): 7:0 SVI1_PLANE0_TEL_IDD_MAX 24:16 SVI1_PLANE0_TEL_VDD_MAX SMUSVI1_PLANE0_TEL_MIN (smn_addr_map:0x5a0d4,iod_smn_addr_map:0x5a0d4) 32bit (R): 7:0 SVI1_PLANE0_TEL_IDD_MIN 24:16 SVI1_PLANE0_TEL_VDD_MIN SMUSVI1_PLANE0_TEL_SAMPLE_CNT (smn_addr_map:0x5a0c8,iod_smn_addr_map:0x5a0c8) 32bit (R): 9:0 SVI1_PLANE0_TEL_SAMPLE_CNT SMUSVI1_PLANE0_TEL_VDD_SUM (smn_addr_map:0x5a0d0,iod_smn_addr_map:0x5a0d0) 32bit (R): 18:0 SVI1_PLANE0_TEL_VDD_SUM SMUSVI1_PLANE0_VIDCHGBUSY (smn_addr_map:0x5a048,iod_smn_addr_map:0x5a048) 32bit (R): 0 SVI1_PLANE0_VID_CHGBUSY SMUSVI1_PLANE1_CURRENTVID (smn_addr_map:0x5a05c,iod_smn_addr_map:0x5a05c) 32bit (R): 31:24 CURRENT_SVI1_PLANE1_VID SMUSVI1_PLANE1_TEL_IDD_SUM (smn_addr_map:0x5a0e0,iod_smn_addr_map:0x5a0e0) 32bit (R): 17:0 SVI1_PLANE1_TEL_IDD_SUM SMUSVI1_PLANE1_TEL_MAX (smn_addr_map:0x5a0ec,iod_smn_addr_map:0x5a0ec) 32bit (R): 7:0 SVI1_PLANE1_TEL_IDD_MAX 24:16 SVI1_PLANE1_TEL_VDD_MAX SMUSVI1_PLANE1_TEL_MIN (smn_addr_map:0x5a0e8,iod_smn_addr_map:0x5a0e8) 32bit (R): 7:0 SVI1_PLANE1_TEL_IDD_MIN 24:16 SVI1_PLANE1_TEL_VDD_MIN SMUSVI1_PLANE1_TEL_SAMPLE_CNT (smn_addr_map:0x5a0dc,iod_smn_addr_map:0x5a0dc) 32bit (R): 9:0 SVI1_PLANE1_TEL_SAMPLE_CNT SMUSVI1_PLANE1_TEL_VDD_SUM (smn_addr_map:0x5a0e4,iod_smn_addr_map:0x5a0e4) 32bit (R): 18:0 SVI1_PLANE1_TEL_VDD_SUM SMUSVI1_PLANE1_VIDCHGBUSY (smn_addr_map:0x5a04c,iod_smn_addr_map:0x5a04c) 32bit (R): 0 SVI1_PLANE1_VID_CHGBUSY SMUSVI1_PLANE_VIDCHG (smn_addr_map:0x5a034,iod_smn_addr_map:0x5a034) 32bit: 1:0 SVI1_VIDPLANE 5 SVI1_VIDCHGZEROVID 6 SVI1_VIDCHGRAMP 9:7 SVI1_VSTIME 23:16 SVI1_VID SMUSVI1_PSI0 (smn_addr_map:0x5a024,iod_smn_addr_map:0x5a024) 32bit: 7:0 SVI1_PLANE0_PSI_VID 8 SVI1_PLANE0_PSI_VID_EN 19:12 SVI1_PLANE1_PSI_VID 20 SVI1_PLANE1_PSI_VID_EN SMUSVI1_TEL_PLANE0 (smn_addr_map:0x5a014,iod_smn_addr_map:0x5a014) 32bit (R): 7:0 SVI1_PLANE0_IDDCOR 24:16 SVI1_PLANE0_VDDCOR SMUSVI1_TEL_PLANE1 (smn_addr_map:0x5a018,iod_smn_addr_map:0x5a018) 32bit (R): 7:0 SVI1_PLANE1_IDDCOR 24:16 SVI1_PLANE1_VDDCOR SMUSVI1_TFN (smn_addr_map:0x5a020,iod_smn_addr_map:0x5a020) 32bit: 0 SVI1_TFN_PLANE0 1 SVI1_TFN_PLANE1 SMUSVI_ALL_CPU_IN_CC6 (smn_addr_map:0x5a060,iod_smn_addr_map:0x5a060) 32bit: 0 ALL_CPU_IN_CC6 SMUSVI_BOOTVID (smn_addr_map:0x5a064,iod_smn_addr_map:0x5a064) 32bit (R): 0 BOOTSVD_VR0 1 BOOTSVC_VR0 2 BOOTSVD_VR1 3 BOOTSVC_VR1 8 SVI0_PLANE1_STARTUP_COMPL_EN 9 SVI0_PLANE0_STARTUP_COMPL_EN 10 SVI1_PLANE0_STARTUP_COMPL_EN 11 SVI1_PLANE1_STARTUP_COMPL_EN SMUSVI_PLANE_MAP (smn_addr_map:0x5a090,iod_smn_addr_map:0x5a090) 32bit: 1:0 SVI0_PLANE0_MAP 5:4 SVI0_PLANE1_MAP 9:8 SVI1_PLANE0_MAP 13:12 SVI1_PLANE1_MAP SMUSVI_PLANE_USAGE (smn_addr_map:0x5a088,iod_smn_addr_map:0x5a088) 32bit: 0 SVI0_PLANE0_USAGE 1 SVI0_PLANE1_USAGE 2 SVI1_PLANE0_USAGE 3 SVI1_PLANE1_USAGE SMUSVI_STARTUP_VID_COMPLETE (smn_addr_map:0x5a068,iod_smn_addr_map:0x5a068) 32bit (R): 0 STARTUP_SVI1_PLANE0_COMPLETE 1 STARTUP_SVI0_PLANE0_COMPLETE 2 STARTUP_SVI0_PLANE1_COMPLETE 3 STARTUP_SVI1_PLANE1_COMPLETE SMUSVI_STARTUP_VID_EN (smn_addr_map:0x5a0f0,iod_smn_addr_map:0x5a0f0) 32bit (R): 0 STARTUP_VID_SVI0_EN 4 STARTUP_VID_SVI1_EN SMUSVI_STARTUP_VID_TRIGGER (smn_addr_map:0x5a0f4,iod_smn_addr_map:0x5a0f4) 32bit: 0 STARTUP_VID_SVI0_TRIGGER 4 STARTUP_VID_SVI1_TRIGGER SMUSVI_SVC0 (smn_addr_map:0x5a070,iod_smn_addr_map:0x5a070) 32bit: 1 SCHMEN 2 PU 3 PD 6 S0 7 S1 17 OE_OVERRIDE 18 OE 19 A_OVERRIDE 20 A 31 Y(R) SMUSVI_SVC1 (smn_addr_map:0x5a07c,iod_smn_addr_map:0x5a07c) 32bit: 1 SCHMEN 2 PU 3 PD 6 S0 7 S1 17 OE_OVERRIDE 18 OE 19 A_OVERRIDE 20 A 31 Y(R) SMUSVI_SVD0 (smn_addr_map:0x5a074,iod_smn_addr_map:0x5a074) 32bit: 1 SCHMEN 2 PU 3 PD 6 S0 7 S1 17 OE_OVERRIDE 18 OE 19 A_OVERRIDE 20 A 31 Y(R) SMUSVI_SVD1 (smn_addr_map:0x5a080,iod_smn_addr_map:0x5a080) 32bit: 1 SCHMEN 2 PU 3 PD 6 S0 7 S1 17 OE_OVERRIDE 18 OE 19 A_OVERRIDE 20 A 31 Y(R) SMUSVI_SVT0 (smn_addr_map:0x5a078,iod_smn_addr_map:0x5a078) 32bit: 0 SCHMEN 1 OE 2 PU 3 PD 6 S0 7 S1 20 A 31 Y(R) SMUSVI_SVT1 (smn_addr_map:0x5a084,iod_smn_addr_map:0x5a084) 32bit: 0 SCHMEN 1 OE 2 PU 3 PD 6 S0 7 S1 20 A 31 Y(R) SMUSVI_TEL_AVRG_CTRL (smn_addr_map:0x5a094,iod_smn_addr_map:0x5a094) 32bit: 0 SVI0_PLANE0_TEL_AVRG_EN 4 SVI0_PLANE1_TEL_AVRG_EN 8 SVI1_PLANE0_TEL_AVRG_EN 12 SVI1_PLANE1_TEL_AVRG_EN 16 TEL_REFCLK_CNTEN SMUSVI_TEL_AVRG_SAMPLE (smn_addr_map:0x5a098,iod_smn_addr_map:0x5a098) 32bit: 0 TEL_AVRG_SAMPLE SMUSVI_TEL_REFCLK_CNT (smn_addr_map:0x5a09c,iod_smn_addr_map:0x5a09c) 32bit (R): 22:0 TEL_REFCLK_CNT 23 TEL_REFCLK_CNT_OVERFLOW SMUSVI_WARMRESET_SEL (smn_addr_map:0x5a03c,iod_smn_addr_map:0x5a03c) 32bit: 1:0 SVI0_PLANE0_WARMRESET_SEL 3:2 SVI0_PLANE1_WARMRESET_SEL 5:4 SVI1_PLANE0_WARMRESET_SEL 7:6 SVI1_PLANE1_WARMRESET_SEL SMUSVI_WARMRESET_TARGET_VID (smn_addr_map:0x5a038,iod_smn_addr_map:0x5a038) 32bit: 7:0 SVI0_PLANE0_WARMRESET_TAGET_VID 15:8 SVI0_PLANE1_WARMRESET_TAGET_VID 23:16 SVI1_PLANE0_WARMRESET_TAGET_VID 31:24 SVI1_PLANE1_WARMRESET_TAGET_VID SMUSVI_WARM_RESET (smn_addr_map:0x5a06c,iod_smn_addr_map:0x5a06c) 32bit: 0 WARM_RESET_SVI0 4 WARM_RESET_SVI1