library IEEE;

entity somador_completo is
	port(c_in,x,y	: in bit;
		sum, c_out	: out bit);
end somador_completo;

architecture somador_completo_op1 of somador_completo is
	begin
	sum <= c_in xor (x xor y);
	c_out <= ((x xor y) and c_in) or (x and y);
end somador_completo_op1;

--architecture somador_completo_op2 of somador_completo is
--	signal s1,s2,s3 	: bit;
--	begin
--	s1 <= (x xor y ) after 20 ns;
--	s2 <= (c_in and s1) after 20 ns;
--	s3 <= (x and y) after 20 ns;
--end somador_completo_op2;

entity sum_3bits is
	port(
		C_in:	in bit;
		a,b:	in bit_vector(2 downto 0);
		Sum:	out bit_vector(2 downto 0);
		C_out:	out bit
		);
end sum_3bits;

architecture sum_3bits_op of sum_3bits is
	component somador_completo
		port(c_in,x,y: in bit;
			sum,c_out:	out bit
			);
	end component;
	signal t1,t2: bit; --signal temporario
	begin
		FA1: somador_completo port map(C_in,a(0),b(0),Sum(0),t1);
		FA2: somador_completo port map(t1,a(1),b(1),Sum(1),t2);
		FA3: somador_completo port map(t2,a(2),b(2),Sum(2),C_out);
end sum_3bits_op;

entity simulador_3bits is
end simulador_3bits;

architecture simulador_3bits_op of simulador_3bits is
	signal x_sim,y_sim,sum :	bit_vector(2 downto 0);
	signal c_in,c_out :	bit;
	component sum_3bits
		port(
		C_in:	in bit;
		a,b:	in bit_vector(2 downto 0);
		Sum:	out bit_vector(2 downto 0);
		C_out:	out bit
		);
	end component;
	begin
		PORT1: sum_3bits port map(C_in=>c_in,a=>x_sim,b=>y_sim,Sum=>sum,C_out=>c_out);
		process
		begin
				x_sim<="000";
				y_sim<="000"; 
				c_in <= '0';
				wait for 20 ns;
				x_sim<="000";
				y_sim<="000"; 
				c_in <= '1';
				wait for 20 ns;
				x_sim<="000";
				y_sim<="111"; 
				c_in <= '1';
				wait for 20 ns;
				x_sim<="110";
				y_sim<="100"; 
				c_in <= '1';
				wait for 20 ns;
				x_sim<="111";
				y_sim<="000"; 
				c_in <= '1';
				wait for 20 ns;
				x_sim<="011";
				y_sim<="101"; 
				c_in <= '1';
				wait for 20 ns;
				x_sim<="001";
				y_sim<="110"; 
				c_in <= '0';
				wait for 20 ns;
				x_sim<="111";
				y_sim<="111"; 
				c_in <= '0';
				wait for 20 ns;
				x_sim<="000";
				y_sim<="100"; 
				c_in <= '0';
				wait for 20 ns;
				x_sim<="101";
				y_sim<="110"; 
				c_in <= '1';
				wait for 20 ns;
				wait;
		end process;
end simulador_3bits_op;