// NOTE: this example is not compatible with the new branches that have overlays-support #include "am5729-beagleboneai.dts" #include "bbai-pins.h" // https://pastebin.com/vwn4m7Nf &{/chosen} { base_dtb = "bbai-mcspi2"; // <-- name of this file goes here }; &{/aliases} { // these ought to be in dra7.dtsi but they're missing. // they assign spi bus numbers to the spi controller devices. // note that dra7.dtsi assigns spi0 to be &qspi. spi1 = &mcspi1; spi2 = &mcspi2; spi3 = &mcspi3; spi4 = &mcspi4; }; &dra7_pmx_core { mcspi2_pins: mcspi2 { pinctrl-single,pins = < // McSPI clock pin _must_ be configured as PIN_INPUT or the peripheral will not work. // ("PIN_INPUT" means input-enabled while "PIN_OUTPUT" means input-disabled. It has no // influence on output-enable, which is controlled by the peripheral it's muxed to.) DRA7XX_CORE_IOPAD( P9_22B, PIN_INPUT_PULLUP | MUX_MODE0 ) // clock DRA7XX_CORE_IOPAD( P9_21B, PIN_INPUT_PULLUP | MUX_MODE0 ) // d1 / data in (miso) DRA7XX_CORE_IOPAD( P9_18A, PIN_OUTPUT_PULLUP | MUX_MODE0 ) // d0 / data out (mosi) DRA7XX_CORE_IOPAD( P9_17A, PIN_OUTPUT_PULLUP | MUX_MODE0 ) // cs 0 // A/B pairs indicate two processor pins connecting to the same expansion header pin. // It's a good idea to always claim both processor pins for any expansion header pin // you use. For the unused processor pin use either PIN_OUTPUT | MUX_MODE15 to // disable the pin, or if the pin supports gpio mode you could select that using // PIN_INPUT | MUX_MODE14 to be able to monitor the pin. DRA7XX_CORE_IOPAD( P9_22A, PIN_OUTPUT | MUX_MODE15 ) DRA7XX_CORE_IOPAD( P9_21A, PIN_OUTPUT | MUX_MODE15 ) DRA7XX_CORE_IOPAD( P9_18B, PIN_OUTPUT | MUX_MODE15 ) DRA7XX_CORE_IOPAD( P9_17B, PIN_OUTPUT | MUX_MODE15 ) >; }; }; &mcspi2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcspi2_pins>; ti,spi-num-cs = <2>; // number of chip selects used channel@0 { reg = <0>; compatible = "spidev"; symlink = "spi/2.0"; // create symlink at /dev/spi/2.0 // FIXME - replace by actual max frequency of device spi-max-frequency = <48000000>; // defaults to SPI mode 0 }; channel@1 { reg = <1>; compatible = "spidev"; symlink = "spi/2.1"; // create symlink at /dev/spi/2.1 // FIXME - replace by actual max frequency of device spi-max-frequency = <48000000>; // EXAMPLE - this selects SPI mode 3 (unless overridden by userspace) spi-cpol; spi-cpha; }; }; // Here's the obnoxious part: since u-boot doesn't have sane pin defaults yet, all pins not // explicitly setup above should be overridden here. This will eventually no longer be needed. &cape_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD( P9_11A, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio DRA7XX_CORE_IOPAD( P9_11B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_12, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_13, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio DRA7XX_CORE_IOPAD( P9_14, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_15, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_16, PIN_INPUT_PULLDOWN | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_17A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_17B, PIN_INPUT | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_18A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_18B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_19A, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_19B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_20A, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_20B, PIN_INPUT | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_21A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_21B, PIN_INPUT | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_22A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) // DRA7XX_CORE_IOPAD( P9_22B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_23, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_24, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_25, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_26A, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_26B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_27A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_27B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_28, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_29A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_29B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_30, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_31A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_31B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_41A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_41B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_42A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P9_42B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_03, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_04, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_05, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_06, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_07, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_08, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_09, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_10, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_11, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_12, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_13, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_14, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_15A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_15B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_16, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_17, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_18, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_19, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_20, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_21, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_22, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_23, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_24, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_25, PIN_INPUT_PULLUP | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_26, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_27A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_27B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_28A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_28B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_29A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_29B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_30A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_30B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_31A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_31B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio DRA7XX_CORE_IOPAD( P8_32A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_32B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio DRA7XX_CORE_IOPAD( P8_33A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_33B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_34A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_34B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_35A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_35B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_36A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_36B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_37A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_37B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio DRA7XX_CORE_IOPAD( P8_38A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_38B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio DRA7XX_CORE_IOPAD( P8_39, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_40, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_41, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_42, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_43, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_44, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_45A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_45B, PIN_INPUT | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_46A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) DRA7XX_CORE_IOPAD( P8_46B, PIN_INPUT | MUX_MODE14 ) >; };