- BLOCK_NAME: 'THM' - DESCRIPTION: 'Thermal (THM)' Registers: CG_MULT_THERMAL_CTRL (smn_addr_map:0x59978,iod_smn_addr_map:0x59978) 32bit: 3:0 TS_FILTER - 0: None - 1: F(n) = (T(n) + F(n-1))/2 8:4 UNUSED 9 THERMAL_RANGE_RST 27:20 TEMP_SEL CG_MULT_THERMAL_STATUS (smn_addr_map:0x5997c,iod_smn_addr_map:0x5997c) 32bit (R): 8:0 ASIC_MAX_TEMP 17:9 CTF_TEMP CG_THERMAL_RANGE (smn_addr_map:0x59980,iod_smn_addr_map:0x59980) 32bit (R): 8:0 ASIC_T_MAX 24:16 ASIC_T_MIN SBRMI_APIC_STATUS0 (smn_addr_map:0x59b54,iod_smn_addr_map:0x59b54) 32bit: 31:0 APICStat0 SBRMI_APIC_STATUS1 (smn_addr_map:0x59b58,iod_smn_addr_map:0x59b58) 32bit: 31:0 APICStat1 SBRMI_APIC_STATUS2 (smn_addr_map:0x59b64,iod_smn_addr_map:0x59b64) 32bit: 31:0 APICStat2 SBRMI_APIC_STATUS3 (smn_addr_map:0x59b68,iod_smn_addr_map:0x59b68) 32bit: 31:0 APICStat3 SBRMI_COMMAND (smn_addr_map:0x59b30,iod_smn_addr_map:0x59b30) 32bit: 7:0 Command(R) 15:8 WrDataLen(R) 23:16 RdDataLen(R) 24 CommandSent 25 CommandNotSupported 26 CommandAborted 31:28 Status SBRMI_CONTROL (smn_addr_map:0x59b2c,iod_smn_addr_map:0x59b2c) 32bit: 0 READ_CMD_INT_DIS 1 DPD 2 DbrdySts SBRMI_CORE_EN_NUMBER (smn_addr_map:0x59b48,iod_smn_addr_map:0x59b48) 32bit: 7:0 EnabledCoreNum SBRMI_CORE_EN_STATUS0 (smn_addr_map:0x59b4c,iod_smn_addr_map:0x59b4c) 32bit: 31:0 CoreEnStat0 SBRMI_CORE_EN_STATUS1 (smn_addr_map:0x59b50,iod_smn_addr_map:0x59b50) 32bit: 31:0 CoreEnStat1 SBRMI_CORE_EN_STATUS2 (smn_addr_map:0x59b5c,iod_smn_addr_map:0x59b5c) 32bit: 31:0 CoreEnStat2 SBRMI_CORE_EN_STATUS3 (smn_addr_map:0x59b60,iod_smn_addr_map:0x59b60) 32bit: 31:0 CoreEnStat3 SBRMI_MCE_STATUS0 (smn_addr_map:0x59b6c,iod_smn_addr_map:0x59b6c) 32bit: 31:0 MceStat0 SBRMI_MCE_STATUS1 (smn_addr_map:0x59b70,iod_smn_addr_map:0x59b70) 32bit: 31:0 MceStat1 SBRMI_MCE_STATUS2 (smn_addr_map:0x59b74,iod_smn_addr_map:0x59b74) 32bit: 31:0 MceStat2 SBRMI_MCE_STATUS3 (smn_addr_map:0x59b78,iod_smn_addr_map:0x59b78) 32bit: 31:0 MceStat3 SBRMI_READ_DATA0 (smn_addr_map:0x59b40,iod_smn_addr_map:0x59b40) 32bit: 7:0 RdByte0 15:8 RdByte1 23:16 RdByte2 31:24 RdByte3 SBRMI_READ_DATA1 (smn_addr_map:0x59b44,iod_smn_addr_map:0x59b44) 32bit: 7:0 RdByte4 15:8 RdByte5 23:16 RdByte6 31:24 RdByte7 SBRMI_WRITE_DATA0 (smn_addr_map:0x59b34,iod_smn_addr_map:0x59b34) 32bit (R): 7:0 WrByte0 15:8 WrByte1 23:16 WrByte2 31:24 WrByte3 SBRMI_WRITE_DATA1 (smn_addr_map:0x59b38,iod_smn_addr_map:0x59b38) 32bit (R): 7:0 WrByte4 15:8 WrByte5 23:16 WrByte6 31:24 WrByte7 SBRMI_WRITE_DATA2 (smn_addr_map:0x59b3c,iod_smn_addr_map:0x59b3c) 32bit (R): 7:0 WrByte8 15:8 WrByte9 23:16 WrByte10 31:24 WrByte11 SBTSI_REMOTE_TEMP (smn_addr_map:0x59b28,iod_smn_addr_map:0x59b28) 32bit: 10:0 RemoteTcenSensor 18:11 RemoteTcenSensorId 19 RemoteTcenSensorValid SMBUS_BLKRD_CMD_CTRL0 (smn_addr_map:0x59b8c,iod_smn_addr_map:0x59b8c) 32bit: 7:0 SMB_BLK_RD_CMD0 15:8 SMB_BLK_RD_CMD1 23:16 SMB_BLK_RD_CMD2 31:24 SMB_BLK_RD_CMD3 SMBUS_BLKRD_CMD_CTRL1 (smn_addr_map:0x59b90,iod_smn_addr_map:0x59b90) 32bit: 7:0 SMB_BLK_RD_CMD4 15:8 SMB_BLK_RD_CMD5 23:16 SMB_BLK_RD_CMD6 31:24 SMB_BLK_RD_CMD7 SMBUS_BLKWR_CMD_CTRL0 (smn_addr_map:0x59b84,iod_smn_addr_map:0x59b84) 32bit: 7:0 SMB_BLK_WR_CMD0 15:8 SMB_BLK_WR_CMD1 23:16 SMB_BLK_WR_CMD2 31:24 SMB_BLK_WR_CMD3 SMBUS_BLKWR_CMD_CTRL1 (smn_addr_map:0x59b88,iod_smn_addr_map:0x59b88) 32bit: 7:0 SMB_BLK_WR_CMD4 15:8 SMB_BLK_WR_CMD5 23:16 SMB_BLK_WR_CMD6 31:24 SMB_BLK_WR_CMD7 SMBUS_CNTL0 (smn_addr_map:0x59b7c,iod_smn_addr_map:0x59b7c) 32bit: 0 SMB_DEFAULT_SLV_ADDR_OVERRIDE 7:1 SMB_DEFAULT_SLV_ADDR 15:8 SMB_CPL_DUMMY_BYTE 18:16 SMB_NOTIFY_ARP_MAX_TIMES 20 THM_READY(R) SMBUS_CNTL1 (smn_addr_map:0x59b80,iod_smn_addr_map:0x59b80) 32bit: 0 SMB_TIMEOUT_EN 8:1 SMB_BLK_WR_CMD_EN 16:9 SMB_BLK_RD_CMD_EN SMBUS_TIMING_CNTL0 (smn_addr_map:0x59b94,iod_smn_addr_map:0x59b94) 32bit: 21:0 SMB_TIMEOUT_MARGIN 29:22 SMB_FILTER_LEVEL_CONVERT_MARGIN SMBUS_TIMING_CNTL1 (smn_addr_map:0x59b98,iod_smn_addr_map:0x59b98) 32bit: 4:0 SMB_DAT_SETUP_TIME_MARGIN 10:5 SMB_DAT_HOLD_TIME_MARGIN 19:11 SMB_START_AND_STOP_TIMING_MARGIN 29:20 SMB_BUS_FREE_MARGIN SMBUS_TIMING_CNTL2 (smn_addr_map:0x59b9c,iod_smn_addr_map:0x59b9c) 32bit: 12:0 SMB_SMBCLK_HIGHMAX_MARGIN 26:13 SMBCLK_LEVEL_CTRL_MARGIN SMBUS_TRIGGER_CNTL (smn_addr_map:0x59ba0,iod_smn_addr_map:0x59ba0) 32bit: 0 SMB_SOFT_RESET_TRIGGER 8 SMB_NOTIFY_ARP_TRIGGER SMBUS_UDID_CNTL0 (smn_addr_map:0x59ba4,iod_smn_addr_map:0x59ba4) 32bit: 30:0 SMB_PRBS_INI_SEED 31 SMB_SRST_REGEN_UDID_EN SMBUS_UDID_CNTL1 (smn_addr_map:0x59ba8,iod_smn_addr_map:0x59ba8) 32bit: 31:0 SMB_UDID_31_0 SMBUS_UDID_CNTL2 (smn_addr_map:0x59bac,iod_smn_addr_map:0x59bac) 32bit: 0 PEC_SUPPORTED 3:1 UDID_VERSION 7:4 SMBUS_VERSION 8 OEM 9 ASF 10 IPMI SMUSBI_ALERT (smn_addr_map:0x59bb4,iod_smn_addr_map:0x59bb4) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) SMUSBI_CKNBIRESET (smn_addr_map:0x59b1c,iod_smn_addr_map:0x59b1c) 32bit: 0 CKNBIRESET SMUSBI_ERRATA_STAT_REG (smn_addr_map:0x59b14,iod_smn_addr_map:0x59b14) 32bit (R): 31:0 ERRATA_STAT_REG SMUSBI_HS_TIMING (smn_addr_map:0x59b24,iod_smn_addr_map:0x59b24) 32bit: 5:0 HS_SETUP_TIME 8 HS_SETUP_TIME_OVERRIDE 23:16 HS_HOLD_TIME 24 HS_HOLD_TIME_OVERRIDE SMUSBI_IOD0_CCD_SIC (smn_addr_map:0x59bb8,iod_smn_addr_map:0x59bb8) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) SMUSBI_IOD0_CCD_SID (smn_addr_map:0x59bbc,iod_smn_addr_map:0x59bbc) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) SMUSBI_IOD0_CCD_SIDIN (smn_addr_map:0x59bc0,iod_smn_addr_map:0x59bc0) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) SMUSBI_IOD1_CCD_SIC (smn_addr_map:0x59bc4,iod_smn_addr_map:0x59bc4) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) SMUSBI_IOD1_CCD_SID (smn_addr_map:0x59bc8,iod_smn_addr_map:0x59bc8) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) SMUSBI_IOD1_CCD_SIDIN (smn_addr_map:0x59bcc,iod_smn_addr_map:0x59bcc) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) SMUSBI_MP0_CTRL (smn_addr_map:0x59b10,iod_smn_addr_map:0x59b10) 32bit: 0 MP0_ALERT 1 APML_EN 2 TSI_EN 3 SBAXI_THM_REG_ONLY SMUSBI_MP0_SBIREGADDR (smn_addr_map:0x59b08,iod_smn_addr_map:0x59b08) 32bit: 7:0 SBI_MP0_REGADDR SMUSBI_MP0_SBIREGDATA (smn_addr_map:0x59b0c,iod_smn_addr_map:0x59b0c) 32bit: 31:0 SBI_MP0_REGDATA SMUSBI_SBICTRL (smn_addr_map:0x59b18,iod_smn_addr_map:0x59b18) 32bit: 0 CK_SPRSBIWRDONE(R) 1 NB_SBISELECT 4:2 NB_SBIADDR 5 NB_SBIADDR_OVERRIDE SMUSBI_SBIREGADDR (smn_addr_map:0x59b00,iod_smn_addr_map:0x59b00) 32bit: 10:0 SBI_REGADDR SMUSBI_SBIREGDATA (smn_addr_map:0x59b04,iod_smn_addr_map:0x59b04) 32bit: 31:0 SBI_REGDATA SMUSBI_SMBUS (smn_addr_map:0x59bb0,iod_smn_addr_map:0x59bb0) 32bit: 0 Spare0 1 Spare1 2 ResBiasEn 3 CompSel 7:4 NG 9:8 I2cRxSel 10 PdEn0 11 PdEn1 13:12 FallSlewSel 14 Slewn 15 SpikeRcEn 16 SpikeRcSel 17 CSel0p9 18 CSel1p1 19 RSel0p9 20 RSel1p1 21 BiasCrtEn 22 DI2C0 23 DI2C1 24 DI2C0_OVERRIDE 25 DI2C1_OVERRIDE 30 Y0(R) 31 Y1(R) SMUSBI_TIMING (smn_addr_map:0x59b20,iod_smn_addr_map:0x59b20) 32bit: 5:0 SETUP_TIME 8 SETUP_TIME_OVERRIDE 23:16 HOLD_TIME 24 HOLD_TIME_OVERRIDE 27 DGLT_LMT_OVERRIDE 31:28 DGLT_LMT THM_CTF_DELAY (smn_addr_map:0x5980c,iod_smn_addr_map:0x5980c) 32bit: 19:0 CTF_DELAY_CNT THM_DIE1_TEMP (smn_addr_map:0x59954,iod_smn_addr_map:0x59954) 32bit: 10:0 TEMP 11 VALID THM_DIE2_TEMP (smn_addr_map:0x59958,iod_smn_addr_map:0x59958) 32bit: 10:0 TEMP 11 VALID THM_DIE3_TEMP (smn_addr_map:0x5995c,iod_smn_addr_map:0x5995c) 32bit: 10:0 TEMP 11 VALID THM_DIE4_TEMP (smn_addr_map:0x59960,iod_smn_addr_map:0x59960) 32bit: 10:0 TEMP 11 VALID THM_DIE5_TEMP (smn_addr_map:0x59964,iod_smn_addr_map:0x59964) 32bit: 10:0 TEMP 11 VALID THM_DIE6_TEMP (smn_addr_map:0x59968,iod_smn_addr_map:0x59968) 32bit: 10:0 TEMP 11 VALID THM_DIE7_TEMP (smn_addr_map:0x5996c,iod_smn_addr_map:0x5996c) 32bit: 10:0 TEMP 11 VALID THM_DIE8_TEMP (smn_addr_map:0x59970,iod_smn_addr_map:0x59970) 32bit: 10:0 TEMP 11 VALID THM_DT0_0_COEFF (smn_addr_map:0x59a2c,iod_smn_addr_map:0x59a2c) 32bit: 6:0 Dt0_1 13:7 Dt0_2 20:14 Dt0_3 27:21 Dt0_4 THM_DT0_1_COEFF (smn_addr_map:0x59a30,iod_smn_addr_map:0x59a30) 32bit: 6:0 Dt0_5 13:7 Dt0_6 20:14 Dt0_7 27:21 Dt0_8 THM_DT0_2_COEFF (smn_addr_map:0x59a34,iod_smn_addr_map:0x59a34) 32bit: 6:0 Dt0_9 13:7 Dt0_10 20:14 Dt0_11 27:21 Dt0_12 THM_DT0_3_COEFF (smn_addr_map:0x59a38,iod_smn_addr_map:0x59a38) 32bit: 6:0 Dt0_13 13:7 Dt0_14 20:14 Dt0_15 27:21 Dt0_16 THM_DT0_4_COEFF (smn_addr_map:0x59a3c,iod_smn_addr_map:0x59a3c) 32bit: 6:0 Dt0_17 13:7 Dt0_18 20:14 Dt0_19 27:21 Dt0_20 THM_DT0_5_COEFF (smn_addr_map:0x59a40,iod_smn_addr_map:0x59a40) 32bit: 6:0 Dt0_21 13:7 Dt0_22 20:14 Dt0_23 27:21 Dt0_24 THM_DT0_6_COEFF (smn_addr_map:0x59a44,iod_smn_addr_map:0x59a44) 32bit: 6:0 Dt0_25 13:7 Dt0_26 20:14 Dt0_27 27:21 Dt0_28 THM_DT0_7_COEFF (smn_addr_map:0x59a48,iod_smn_addr_map:0x59a48) 32bit: 6:0 Dt0_29 13:7 Dt0_30 20:14 Dt0_31 THM_DT1_0_COEFF (smn_addr_map:0x59a4c,iod_smn_addr_map:0x59a4c) 32bit: 6:0 Dt1_1 13:7 Dt1_2 20:14 Dt1_3 27:21 Dt1_4 THM_DT1_1_COEFF (smn_addr_map:0x59a50,iod_smn_addr_map:0x59a50) 32bit: 6:0 Dt1_5 13:7 Dt1_6 20:14 Dt1_7 27:21 Dt1_8 THM_DT1_2_COEFF (smn_addr_map:0x59a54,iod_smn_addr_map:0x59a54) 32bit: 6:0 Dt1_9 13:7 Dt1_10 20:14 Dt1_11 27:21 Dt1_12 THM_DT1_3_COEFF (smn_addr_map:0x59a58,iod_smn_addr_map:0x59a58) 32bit: 6:0 Dt1_13 13:7 Dt1_14 20:14 Dt1_15 27:21 Dt1_16 THM_DT1_4_COEFF (smn_addr_map:0x59a5c,iod_smn_addr_map:0x59a5c) 32bit: 6:0 Dt1_17 13:7 Dt1_18 20:14 Dt1_19 27:21 Dt1_20 THM_DT1_5_COEFF (smn_addr_map:0x59a60,iod_smn_addr_map:0x59a60) 32bit: 6:0 Dt1_21 13:7 Dt1_22 20:14 Dt1_23 27:21 Dt1_24 THM_DT1_6_COEFF (smn_addr_map:0x59a64,iod_smn_addr_map:0x59a64) 32bit: 6:0 Dt1_25 13:7 Dt1_26 20:14 Dt1_27 27:21 Dt1_28 THM_DT1_7_COEFF (smn_addr_map:0x59a68,iod_smn_addr_map:0x59a68) 32bit: 6:0 Dt1_29 13:7 Dt1_30 20:14 Dt1_31 THM_GPIO_IOD0_CCD_THERMTRIP_L_CTRL (smn_addr_map:0x59a24,iod_smn_addr_map:0x59a24) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) THM_GPIO_IOD1_CCD_THERMTRIP_L_CTRL (smn_addr_map:0x59a28,iod_smn_addr_map:0x59a28) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) THM_GPIO_PROCHOT_CTRL (smn_addr_map:0x59810,iod_smn_addr_map:0x59810) 32bit: 0 TXIMPSEL 1 PD 2 PU 3 SCHMEN 4 S0 5 S1 6 RXEN 7 RXSEL0 8 RXSEL1 16 OE_OVERRIDE 17 OE 18 A_OVERRIDE 19 A 31 Y(R) THM_PWRMGT (smn_addr_map:0x59a1c,iod_smn_addr_map:0x59a1c) 32bit: 0 CLK_GATE_EN 1 CLK_GATE_ST(R) 2 DBG_CLK_GATE_EN 23:8 CLK_GATE_MAX_CNT THM_SW_TEMP (smn_addr_map:0x59974,iod_smn_addr_map:0x59974) 32bit: 8:0 SW_TEMP THM_TCON_CUR_TMP (smn_addr_map:0x59800,iod_smn_addr_map:0x59800) 32bit: 4:0 PER_STEP_TIME_UP 6:5 TMP_MAX_DIFF_UP 7 TMP_SLEW_DN_EN 12:8 PER_STEP_TIME_DN 17:16 CUR_TEMP_TJ_SEL 18 CUR_TEMP_TJ_SLEW_SEL 19 CUR_TEMP_RANGE_SEL 20 MCM_EN 31:21 CUR_TEMP THM_TCON_HTC (smn_addr_map:0x59804,iod_smn_addr_map:0x59804) 32bit: 0 HTC_EN 2 EXTERNAL_PROCHOT(R) 3 INTERNAL_PROCHOT(R) 4 HTC_ACTIVE(R) 5 HTC_ACTIVE_LOG 8 HTC_DIAG 9 DIS_PROCHOT_PIN_OUT 10 HTC_TO_IH_EN 11 PROCHOT_TO_IH_EN 14:12 PROCHOT_EVENT_SRC 15 DIS_PROCHOT_PIN_IN 22:16 HTC_TMP_LMT 26:23 HTC_HYST_LMT 28:27 HTC_SLEW_SEL THM_TCON_LOCAL0 (smn_addr_map:0x599cc,iod_smn_addr_map:0x599cc) 32bit: 1 TMON0_PwrDn_Dis 2 TMON1_PwrDn_Dis THM_TCON_LOCAL1 (smn_addr_map:0x599d0,iod_smn_addr_map:0x599d0) 32bit: 0 Turn_Off_TMON0 1 Turn_Off_TMON1 4 PowerDownTmon0(R) 5 PowerDownTmon1(R) THM_TCON_LOCAL10 (smn_addr_map:0x599f4,iod_smn_addr_map:0x599f4) 32bit (R): 7:0 TMON0_Tj_Max_RS_ID THM_TCON_LOCAL11 (smn_addr_map:0x599f8,iod_smn_addr_map:0x599f8) 32bit (R): 10:0 Tj_Max_TMON1 THM_TCON_LOCAL12 (smn_addr_map:0x599fc,iod_smn_addr_map:0x599fc) 32bit (R): 7:0 TMON1_Tj_Max_RS_ID THM_TCON_LOCAL13 (smn_addr_map:0x59a00,iod_smn_addr_map:0x59a00) 32bit (R): 0 boot_done THM_TCON_LOCAL2 (smn_addr_map:0x599d4,iod_smn_addr_map:0x599d4) 32bit: 1:0 TMON_init_delay 3:2 TMON_pwrup_stagger_time 5 short_stagger_count 6 sbtsi_use_corrected 10 temp_read_skip_scale 11 skip_scale_correction THM_TCON_LOCAL3 (smn_addr_map:0x599d8,iod_smn_addr_map:0x599d8) 32bit (R): 10:0 Global_TMAX THM_TCON_LOCAL4 (smn_addr_map:0x599dc,iod_smn_addr_map:0x599dc) 32bit (R): 7:0 Global_TMAX_ID THM_TCON_LOCAL5 (smn_addr_map:0x599e0,iod_smn_addr_map:0x599e0) 32bit (R): 10:0 Global_TMIN THM_TCON_LOCAL6 (smn_addr_map:0x599e4,iod_smn_addr_map:0x599e4) 32bit (R): 7:0 Global_TMIN_ID THM_TCON_LOCAL7 (smn_addr_map:0x599e8,iod_smn_addr_map:0x599e8) 32bit (R): 7:0 THERMID THM_TCON_LOCAL8 (smn_addr_map:0x599ec,iod_smn_addr_map:0x599ec) 32bit (R): 10:0 THERMMAX THM_TCON_LOCAL9 (smn_addr_map:0x599f0,iod_smn_addr_map:0x599f0) 32bit (R): 10:0 Tj_Max_TMON0 THM_TCON_THERM_TRIP (smn_addr_map:0x59808,iod_smn_addr_map:0x59808) 32bit: 0 CTF_PAD_POLARITY 1 THERM_TP(R) 2 CTF_THRESHOLD_EXCEEDED(R) 3 THERM_TP_SENSE(R) 4 RSVD2 5 THERM_TP_EN 13:6 THERM_TP_LMT 30:14 RSVD3 31 SW_THERM_TP THM_THERMAL_INT_CTRL (smn_addr_map:0x5982c,iod_smn_addr_map:0x5982c) 32bit: 7:0 DIG_THERM_INTH 15:8 DIG_THERM_INTL 23:16 TEMP_THRESHOLD 24 THERM_INTH_MASK - 0: Mask Disabled - 1: Mask Enabled 25 THERM_INTL_MASK - 0: Mask Disabled - 1: Mask Enabled 26 THERM_TRIGGER_MASK - 0: Mask Disabled - 1: Mask Enabled 27 THERM_PROCHOT_MASK - 0: Mask Disabled - 1: Mask Enabled 28 THERM_IH_HW_ENA - 0: Firmware controls thermal trigger - 1: TCON_GN_tm_Gtemp controls thermal trigger 31:29 MAX_IH_CREDIT THM_THERMAL_INT_ENA (smn_addr_map:0x59828,iod_smn_addr_map:0x59828) 32bit (W): 0 THERM_INTH_SET - 1: Set thermal L2H interrupt 1 THERM_INTL_SET - 1: Set thermal H2L interrupt 2 THERM_TRIGGER_SET - 1: Set thermal trigger(ThermTrigger) interrupt 3 THERM_INTH_CLR - 1: Clear thermal L2H interrupt 4 THERM_INTL_CLR - 1: Clear thermal H2L interrupt 5 THERM_TRIGGER_CLR - 1: Clear thermal trigger(ThermTrigger) interrupt THM_THERMAL_INT_STATUS (smn_addr_map:0x59830,iod_smn_addr_map:0x59830) 32bit (R): 0 THERM_INTH_DETECT - 1: Thermal L2H interrupt detected 1 THERM_INTL_DETECT - 1: Thermal H2L interrupt detected 2 THERM_TRIGGER_DETECT - 1: Thermal trigger interrupt detected 3 THERM_PROCHOT_DETECT - 1: CNB thermal trigger interrupt detected THM_TMON0_COEFF (smn_addr_map:0x5998c,iod_smn_addr_map:0x5998c) 32bit: 10:0 C_OFFSET 17:11 D THM_TMON0_CTRL (smn_addr_map:0x598b8,iod_smn_addr_map:0x598b8) 32bit: 0 POWER_DOWN 8:1 BGADJ 9 BGADJ_MODE 10 TMON_PAUSE 11 INT_MEAS_EN 12 DEBUG_MODE 13 EN_CFG_SERDES THM_TMON0_CTRL2 (smn_addr_map:0x598bc,iod_smn_addr_map:0x598bc) 32bit: 15:0 RDIL_PRESENT 31:16 RDIR_PRESENT THM_TMON0_DEBUG (smn_addr_map:0x598c0,iod_smn_addr_map:0x598c0) 32bit: 4:0 DEBUG_RDI 15:5 DEBUG_Z THM_TMON0_INT_DATA (smn_addr_map:0x598b4,iod_smn_addr_map:0x598b4) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL0_DATA (smn_addr_map:0x59834,iod_smn_addr_map:0x59834) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL10_DATA (smn_addr_map:0x5985c,iod_smn_addr_map:0x5985c) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL11_DATA (smn_addr_map:0x59860,iod_smn_addr_map:0x59860) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL12_DATA (smn_addr_map:0x59864,iod_smn_addr_map:0x59864) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL13_DATA (smn_addr_map:0x59868,iod_smn_addr_map:0x59868) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL14_DATA (smn_addr_map:0x5986c,iod_smn_addr_map:0x5986c) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL15_DATA (smn_addr_map:0x59870,iod_smn_addr_map:0x59870) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL1_DATA (smn_addr_map:0x59838,iod_smn_addr_map:0x59838) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL2_DATA (smn_addr_map:0x5983c,iod_smn_addr_map:0x5983c) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL3_DATA (smn_addr_map:0x59840,iod_smn_addr_map:0x59840) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL4_DATA (smn_addr_map:0x59844,iod_smn_addr_map:0x59844) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL5_DATA (smn_addr_map:0x59848,iod_smn_addr_map:0x59848) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL6_DATA (smn_addr_map:0x5984c,iod_smn_addr_map:0x5984c) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL7_DATA (smn_addr_map:0x59850,iod_smn_addr_map:0x59850) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL8_DATA (smn_addr_map:0x59854,iod_smn_addr_map:0x59854) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIL9_DATA (smn_addr_map:0x59858,iod_smn_addr_map:0x59858) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR0_DATA (smn_addr_map:0x59874,iod_smn_addr_map:0x59874) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR10_DATA (smn_addr_map:0x5989c,iod_smn_addr_map:0x5989c) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR11_DATA (smn_addr_map:0x598a0,iod_smn_addr_map:0x598a0) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR12_DATA (smn_addr_map:0x598a4,iod_smn_addr_map:0x598a4) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR13_DATA (smn_addr_map:0x598a8,iod_smn_addr_map:0x598a8) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR14_DATA (smn_addr_map:0x598ac,iod_smn_addr_map:0x598ac) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR15_DATA (smn_addr_map:0x598b0,iod_smn_addr_map:0x598b0) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR1_DATA (smn_addr_map:0x59878,iod_smn_addr_map:0x59878) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR2_DATA (smn_addr_map:0x5987c,iod_smn_addr_map:0x5987c) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR3_DATA (smn_addr_map:0x59880,iod_smn_addr_map:0x59880) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR4_DATA (smn_addr_map:0x59884,iod_smn_addr_map:0x59884) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR5_DATA (smn_addr_map:0x59888,iod_smn_addr_map:0x59888) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR6_DATA (smn_addr_map:0x5988c,iod_smn_addr_map:0x5988c) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR7_DATA (smn_addr_map:0x59890,iod_smn_addr_map:0x59890) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR8_DATA (smn_addr_map:0x59894,iod_smn_addr_map:0x59894) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_RDIR9_DATA (smn_addr_map:0x59898,iod_smn_addr_map:0x59898) 32bit (R): 10:0 Z 11 VALID 23:12 TEMP THM_TMON0_REMOTE_END (smn_addr_map:0x59cfc,iod_smn_addr_map:0x59cfc) 32bit: 31:0 DATA THM_TMON0_REMOTE_START (smn_addr_map:0x59c00,iod_smn_addr_map:0x59c00) 32bit: 31:0 DATA THM_TMON1_REMOTE_END (smn_addr_map:0x59dfc,iod_smn_addr_map:0x59dfc) 32bit: 31:0 DATA THM_TMON1_REMOTE_START (smn_addr_map:0x59d00,iod_smn_addr_map:0x59d00) 32bit: 31:0 DATA THM_TMON2_REMOTE_END (smn_addr_map:0x59efc,iod_smn_addr_map:0x59efc) 32bit: 31:0 DATA THM_TMON2_REMOTE_START (smn_addr_map:0x59e00,iod_smn_addr_map:0x59e00) 32bit: 31:0 DATA THM_TMON3_REMOTE_END (smn_addr_map:0x59ffc,iod_smn_addr_map:0x59ffc) 32bit: 31:0 DATA THM_TMON3_REMOTE_START (smn_addr_map:0x59f00,iod_smn_addr_map:0x59f00) 32bit: 31:0 DATA THM_TMON_CONFIG (smn_addr_map:0x59984,iod_smn_addr_map:0x59984) 32bit: 2:0 NUM_ACQ 3 FORCE_MAX_ACQ 4 RDI_INTERLEAVE 5 CONFIG_SOURCE 6 RE_CALIB_EN 31:21 Z THM_TMON_CONFIG2 (smn_addr_map:0x59988,iod_smn_addr_map:0x59988) 32bit: 11:0 A 17:12 B 28:18 C 29 K