library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_unsigned.all;

entity reg_ex2 is
	port(
		D : std_logic_vector(3 downto 0);
		op: std_logic_vector(1 downto 0);
		clk: std_logic;
		left_in: std_logic;
		right_in: std_logic;
		Q: out std_logic_vector(3 downto 0)
	);
end entity;

architecture toto of reg_ex2 is
	signal inside, nextone : std_logic_vector(3 downto 0);
	
begin
	inside <= inside; -- si rien ne se passe, garder la valeur
	
	process (clk, D, op, left_in, right_in)
	begin
		if rising_edge(clk) then
			case op is
				when "00" =>
					null; -- si opcode="00", garder la valeur
				when "01" =>
					inside <= inside(3 downto 1) & right_in; -- left shift
				when "10" =>
					inside <= left_in & inside(2 downto 0); -- right shift
				when "11" =>
					inside <= D; -- stocker la valeur d'entrée
				when others =>
					null; -- ne rien faire (pour terminer le case uniquement)
			end case;
		end if;
	end process;
	
	Q <= inside;
end toto;