--- imx6_ahci.c 2017-07-19 20:12:00.974999000 -0700 +++ /usr/home/russellh/FreeBSD/rh-armv6/src/sys/arm/freescale/imx/imx6_ahci.c 2017-07-19 20:18:18.460702000 -0700 @@ -45,42 +45,44 @@ __FBSDID("$FreeBSD$"); #include #include -#define SATA_P0PHYCR 0x00000178 -#define SATA_P0PHYCR_CR_READ (1 << 19) -#define SATA_P0PHYCR_CR_WRITE (1 << 18) -#define SATA_P0PHYCR_CR_CAP_DATA (1 << 17) -#define SATA_P0PHYCR_CR_CAP_ADDR (1 << 16) -#define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff) -#define SATA_P0PHYSR 0x0000017c -#define SATA_P0PHYSR_CR_ACK (1 << 18) -#define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff) +#define SATA_P0PHYCR 0x00000178 +#define SATA_P0PHYCR_CR_READ (1 << 19) +#define SATA_P0PHYCR_CR_WRITE (1 << 18) +#define SATA_P0PHYCR_CR_CAP_DATA (1 << 17) +#define SATA_P0PHYCR_CR_CAP_ADDR (1 << 16) +#define SATA_P0PHYCR_CR_DATA_IN(v) ((v) & 0xffff) +#define SATA_P0PHYSR 0x0000017c +#define SATA_P0PHYSR_CR_ACK (1 << 18) +#define SATA_P0PHYSR_CR_DATA_OUT(v) ((v) & 0xffff) -#define SATA_TIMER1MS 0x000000e0 +#define SATA_TIMER1MS 0x000000e0 /* phy registers */ -#define SATA_PHY_CLOCK_RESET 0x7f3f -#define SATA_PHY_CLOCK_RESET_RST (1 << 0) +#define SATA_PHY_CLOCK_RESET 0x7f3f +#define SATA_PHY_CLOCK_RESET_RST (1 << 0) -#define SATA_PHY_LANE0_OUT_STAT 0x2003 -#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE (1 << 1) +#define SATA_PHY_LANE0_OUT_STAT 0x2003 +#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE (1 << 1) +//imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, int on) static int -imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, int on) +imx6_ahci_phy_ctrl(struct ahci_controller* sc, uint32_t bitmask, bool on) { uint32_t v; int timeout; v = ATA_INL(sc->r_mem, SATA_P0PHYCR); - if(on) { + if (on) { v |= bitmask; } else { v &= ~bitmask; } ATA_OUTL(sc->r_mem, SATA_P0PHYCR, v); - for(timeout = 5000; timeout > 0; --timeout) { + for (timeout = 5000; timeout > 0; --timeout) { v = ATA_INL(sc->r_mem, SATA_P0PHYSR); - if(!!(v & SATA_P0PHYSR_CR_ACK) == !!on) { + //if (!!(v & SATA_P0PHYSR_CR_ACK) == !!on) { + if ((v & SATA_P0PHYSR_CR_ACK) == on) { break; } DELAY(100); @@ -97,23 +99,19 @@ static int imx6_ahci_phy_addr(struct ahci_controller* sc, uint32_t addr) { int error; + DELAY(100); - ATA_OUTL(sc->r_mem, SATA_P0PHYCR, addr); - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, 1); - if(error != 0) { - if(bootverbose) { - device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n", __FUNCTION__); - } + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, true); + if (error != 0) { + device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=1\n", __FUNCTION__); return error; } - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, 0); - if(error != 0) { - if(bootverbose) { - device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n", __FUNCTION__); - } + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_ADDR, false); + if (error != 0) { + device_printf(sc->dev, "%s: timeout on SATA_P0PHYCR_CR_CAP_ADDR=0\n", __FUNCTION__); return error; } @@ -127,43 +125,39 @@ imx6_ahci_phy_write(struct ahci_controller* sc, uint32 int error; error = imx6_ahci_phy_addr(sc, addr); - if(error != 0) { - if(bootverbose) { device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__); } + if (error != 0) { + device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__); return error; } ATA_OUTL(sc->r_mem, SATA_P0PHYCR, data); - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, 1); - if(error != 0) { - if(bootverbose) { - device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__); - } + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, true); + if (error != 0) { + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=1\n", __FUNCTION__); return error; } - if(imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, 0) != 0) { - if(bootverbose) { - device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__); - } + if (imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_CAP_DATA, false) != 0) { + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_CAP_DATA=0\n", __FUNCTION__); return error; } - if((addr == SATA_PHY_CLOCK_RESET) && data) { + if ((addr == SATA_PHY_CLOCK_RESET) && data) { /* we can't check ACK after RESET */ ATA_OUTL(sc->r_mem, SATA_P0PHYCR, SATA_P0PHYCR_CR_DATA_IN(data) | SATA_P0PHYCR_CR_WRITE); return 0; } - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, 1); - if(error != 0) { - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n", __FUNCTION__); } + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, true); + if (error != 0) { + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=1\n", __FUNCTION__); return error; } - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, 0); - if(error != 0) { - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n", __FUNCTION__); } + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_WRITE, false); + if (error != 0) { + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_WRITE=0\n", __FUNCTION__); return error; } @@ -177,22 +171,22 @@ imx6_ahci_phy_read(struct ahci_controller* sc, uint32_ uint32_t v; error = imx6_ahci_phy_addr(sc, addr); - if(error != 0) { - if(bootverbose) { device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__); } + if (error != 0) { + device_printf(sc->dev, "%s: error on imx6_ahci_phy_addr\n", __FUNCTION__); return error; } - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, 1); - if(error != 0) { - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=1\n", __FUNCTION__); } + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, true); + if (error != 0) { + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=1\n", __FUNCTION__); return error; } v = ATA_INL(sc->r_mem, SATA_P0PHYSR); - error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, 0); - if(error != 0) { - if(bootverbose) { device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=0\n", __FUNCTION__); } + error = imx6_ahci_phy_ctrl(sc, SATA_P0PHYCR_CR_READ, false); + if (error != 0) { + device_printf(sc->dev, "%s: error on SATA_P0PHYCR_CR_READ=0\n", __FUNCTION__); return error; } @@ -202,9 +196,11 @@ imx6_ahci_phy_read(struct ahci_controller* sc, uint32_ static int imx6_ahci_probe(device_t dev) { - if(!ofw_bus_is_compatible(dev, "fsl,imx6q-ahci")) { + if (!ofw_bus_status_okay(dev)) return (ENXIO); - } + if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ahci")) + return (ENXIO); + device_set_desc(dev, "i.MX6 Integrated AHCI controller"); return (BUS_PROBE_DEFAULT); @@ -215,9 +211,7 @@ imx6_ahci_attach(device_t dev) { struct ahci_controller* ctlr; uint32_t v; - int timeout; - int pllstat; - int error; + int error, pllstat, timeout; /* * Init the device PHY @@ -225,7 +219,7 @@ imx6_ahci_attach(device_t dev) ctlr = device_get_softc(dev); error = imx6_ccm_sataphy_enable(); - if(error != 0) { + if (error != 0) { device_printf(dev, "time out resetting AHCI PHY\n"); return error; } @@ -236,54 +230,55 @@ imx6_ahci_attach(device_t dev) ctlr->subdeviceid = 0; ctlr->numirqs = 1; ctlr->r_rid = 0; - if(!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, - &ctlr->r_rid, RF_ACTIVE))) { + + if ((ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &ctlr->r_rid, RF_ACTIVE)) != NULL) return (ENXIO); - } v = imx_iomux_gpr_get(IOMUX_GPR13); - v &= ~(IOMUX_GPR13_SATA_PHY_8(7) | + v &= ~(IOMUX_GPR13_SATA_PHY_8(7) | IOMUX_GPR13_SATA_PHY_7(0x1f) | - IOMUX_GPR13_SATA_PHY_6(7) | - IOMUX_GPR13_SATA_SPEED(1) | - IOMUX_GPR13_SATA_PHY_5(1) | - IOMUX_GPR13_SATA_PHY_4(7) | - IOMUX_GPR13_SATA_PHY_3(0xf) | + IOMUX_GPR13_SATA_PHY_6(7) | + IOMUX_GPR13_SATA_SPEED(1) | + IOMUX_GPR13_SATA_PHY_5(1) | + IOMUX_GPR13_SATA_PHY_4(7) | + IOMUX_GPR13_SATA_PHY_3(0xf) | IOMUX_GPR13_SATA_PHY_2(0x1f) | - IOMUX_GPR13_SATA_PHY_1(1) | + IOMUX_GPR13_SATA_PHY_1(1) | IOMUX_GPR13_SATA_PHY_0(1)); /* setting */ - v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */ - IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */ - IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */ - IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */ - IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */ - IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */ - IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */ - IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */ + v |= IOMUX_GPR13_SATA_PHY_8(5) | /* Rx 3.0db */ + IOMUX_GPR13_SATA_PHY_7(0x12) | /* Rx SATA2m */ + IOMUX_GPR13_SATA_PHY_6(3) | /* Rx DPLL mode */ + IOMUX_GPR13_SATA_SPEED(1) | /* 3.0GHz */ + IOMUX_GPR13_SATA_PHY_5(0) | /* SpreadSpectram */ + IOMUX_GPR13_SATA_PHY_4(4) | /* Tx Attenuation 9/16 */ + IOMUX_GPR13_SATA_PHY_3(0) | /* Tx Boost 0db */ + IOMUX_GPR13_SATA_PHY_2(0x11) | /* Tx Level 1.104V */ IOMUX_GPR13_SATA_PHY_1(1); /* PLL clock enable */ + imx_iomux_gpr_set(IOMUX_GPR13, v); /* phy reset */ error = imx6_ahci_phy_write(ctlr, SATA_PHY_CLOCK_RESET, SATA_PHY_CLOCK_RESET_RST); - if(error != 0) { + if (error != 0) { device_printf(dev, "cannot reset PHY\n"); goto fail; } - for(timeout = 50; timeout > 0; --timeout) { + for (timeout = 50; timeout > 0; --timeout) { DELAY(100); pllstat = imx6_ahci_phy_read(ctlr, SATA_PHY_LANE0_OUT_STAT); - if(pllstat < 0) { + if (pllstat < 0) { device_printf(dev, "cannot read LANE0 status\n"); break; } - if(pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE) { + if (pllstat & SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE) break; - } } - if(timeout <= 0) { + + if (timeout <= 0) { device_printf(dev, "time out reading LANE0 status\n"); error = ETIMEDOUT; goto fail;