-- Declaramos librerías
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Definimos la entidad
entity base is
Port (
A0, A1, A2, A3 : in std_logic; -- Entradas A
B0, B1, B2, B3 : in std_logic; -- Entradas B
mayor, menor, igual : out std_logic -- Salidas
);
end base;
-- Definimos la arquitectura
architecture behavioral of base is
signal A: std_logic_vector(3 downto 0); -- Vector A
signal B: std_logic_vector(3 downto 0); -- Vector B
begin
process(A3, A2, A1, A0)
begin
A(3) <= A3;
A(2) <= A2;
A(1) <= A1;
A(0) <= A0;
end process;
process(B3, B2, B1, B0)
begin
B(3) <= B3;
B(2) <= B2;
B(1) <= B1;
B(0) <= B0;
end process;
mayor <= '1' when(A>B) else '0';
menor <= '1' when(A<B) else '0';
igual <= '1' when(A=B) else '0';
end behavioral;
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